Generally, dummy patterns are inserted into integrated circuit designs to fulfill some design rules. One possible design rule may be to have each layer within the semiconductor device be as uniform as possible to reduce process variations, such as from lithography, etching, chemical mechanical polishing (CMP), or others. For example, dummy active areas may be inserted into a semiconductor material to create more uniform density of active areas in the semiconductor material. Likewise, dummy metal may be inserted into metal layers to cause the metal layers to have a more uniform density. Other dummy patterns may also include cell patterns, polysilicon patterns, or via patterns. Another possible design rule could link the integrated circuit design with a process model for better physical accuracy of the finished device. For example, the rule could require CMP-aware dummy metal insertion for a better physical thickness of the layer.
Designs are typically analyzed for electrical performance of the functional aspects of the integrated circuit using different electronic design automation (EDA) tools. Generally, a rule-based or physical-based dummy insertion is performed by an implementation tool; however, the electrical impact of the dummy pattern on functional components is not considered during this process. Accordingly, generally after the dummy pattern insertion, the performance of functional components are analyzed. Then, interactions of revisions of dummy patterns and re-analysis is generally necessary during the design implementation for optimal device functionality, which can lengthen the design process. Therefore, there is a need in the art to have performance-aware dummy pattern insertion in an integrated circuit.